When in use, some semiconductor devices generate significant quantities of heat. Thermal management techniques are employed to conduct heat away from such semiconductor devices and other components near such semiconductor devices. For example, U.S. Patent Application Pub. No. 2008/0054433, published Mar. 6, 2008, to Yoo et al. discloses a heat transfer blocking spacer interposed between semiconductor chips to prevent transfer of heat from one chip to another. U.S. Pat. No. 7,309,911, issued Dec. 18, 2007, to Bartley et al. discloses a heat sink associated with a stack of platters for cooling a plurality of memory devices. U.S. Pat. No. 6,917,100 discloses multiple stacks of circuit chips that are grouped in groups not active at the same time, and circuit chips belonging to the same group, which are arranged in different layers in adjacent stacks. U.S. Pat. No. 6,747,347, issued Jun. 8, 2004, to Farrar et al. discloses a chip stack hermetically sealed in an enclosure, which includes a pressurized, thermally conductive fluid for cooling the enclosed chip stack. When thermal management techniques used to conduct heat away from heat-generating semiconductor devices are inadequate, the resulting temperatures may degrade performance of such semiconductor devices, may degrade performance of other components near such semiconductor devices, may damage such semiconductor devices, may damage other components near such semiconductor devices, and may even injure a user near that semiconductor device.
Referring to FIG. 4A, a schematic view of a conventional semiconductor device package 100 illustrating flow of heat within the semiconductor device package 100 is shown. The semiconductor device package 100 includes at least one semiconductor device 102 having a heat-generating region 104 such as a region of high power density, for example, a logic die including a high-power SerDes (i.e., Serializer-Deserializer). Additional semiconductor devices 106, such as memory devices (e.g., DRAM devices) are stacked on the semiconductor device 102 having the heat-generating region 104. The semiconductor device 102 having the heat-generating region 104 and the additional semiconductor devices 106 are electrically connected to one another by conductive elements 108 (e.g., conductive bumps, pillars, columns, studs) and conductive vias 109 (e.g., through silicon vias (TSVs)). A thermally conductive overmold 110 covers the semiconductor device 102 having the heat-generating region 104 and the additional stacked semiconductor devices 106. When in use, heat flows from the heat-generating region 104 of the semiconductor device 102 out of the semiconductor device package 100, as indicated by the arrows in FIG. 4A. As heat flows from the heat-generating region 104 out of the semiconductor device package 100, even though heat-generating region 104 is laterally offset from the additional stacked semiconductor devices 106, such heat flows through the thermally conductive overmold 110 not only toward the exterior of semiconductor device package 100, but also to and through the additional stacked semiconductor devices 106. Heat also flows from the heat-generating region 104 through the conductive elements 108 and electrically insulating underfill material between the respective semiconductor devices 102 and 106 and surrounding the conductive elements 108.
Referring to FIG. 4B, an enlarged view of a portion of the semiconductor device package 100 proximate the heat-generating region 104 of the semiconductor device 102 is shown. As indicated by arrows in FIG. 4B, the heat flowing from the heat-generating region 104 of the semiconductor device 104 may flow through the additional semiconductor devices 106 at least in part because the additional semiconductor devices 106 are positioned near the heat-generating region 104 and in contact with thermally conductive overmold 110. In addition, the heat flowing from the heat-generating region 104 may flow through the conductive elements 108 between the semiconductor devices 106 and conductive vias 109 within the additional semiconductor devices 106—at least in part because such conductive elements 108 and conductive vias 109 are positioned near the heat-generating region 104 and because materials of such conductive elements 108 and conductive vias 109 that exhibit high electrical conductance generally also exhibit high thermal conductance. As noted above, the underfill material between each of semiconductor device 102 and semiconductor devices 106 may also act to conduct heat. Thus, heat from the heat-generating region 104 may have a tendency to flow toward and into the additional semiconductor devices 106, and a path of low or even least resistance for the heat to travel out of the semiconductor device package 100 may be through the additional semiconductor devices 106 and the conductive elements 108. As heat flows from heat-generation region 104 through the additional semiconductor devices 106, the temperature of the additional semiconductor devices 106, and particularly of the lowermost semiconductor device 106, may increase to levels sufficient to cause damage to or failure of the additional semiconductor devices 106.